Euromicro Conference on
Digital System Design

August 28 – 30, 2019
Kallithea, Chalkidiki | Greece

DSD 2019

DSD 2019 Call For Papers Committees Submissions Registration

Paper Submission Deadline:

28 April 2019 (extended)

Notification of Acceptance:

3 June 2019

Camera-Ready Papers:

24 June 2019

Dependability, Testing, and Fault Tolerance in Digital Systems (DTFT)

Download the call for papers in pdf format »

Special Session Scope

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from system specification down to micro-architectures, digital circuits and VLSI implementations.

Every designed system has to be tested several times during its life-time - during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault tolerant, etc. The design must reflect these requirements. The special session on "Dependability, Testing, and Fault Tolerance in Digital Systems" (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

Papers on any of the following and related topics can be submitted to the special session:

  • Diagnosis & testing of embedded systems, SoC and NoC testing
  • Memory and CPU testing
  • Analog, mixed-signal and RF, IDDQ and current testing
  • Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
  • Testability analysis, design for testability
  • Error detection and correction, on-line testing, design of checkers
  • Design of dependable (robust) circuits and systems, error mitigation techniques
  • Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
  • FPGA based fault tolerant systems, partial/full reconfiguration based methods
  • Fault injection techniques, fault simulation/emulation
  • Dependability modeling, dependability analysis and validation
  • Formal approaches in fault tolerant systems design
  • System diagnosis
  • Dependable design in practical applications

Special Session Chairs

P. Fišer (CTU in Prague, CZ)

Z. Kotásek (BUT in Brno, CZ)

Special Session Program Committee

P. Bernardi, Politecnico di Torino (IT)

Ch. Bolchini, Politechnico di Milano (IT)

A. Bosio, École Centrale Lyon (FR)

L. Cassano, Politechnico di Milano (IT)

G. Di Natale, LIRMM (FR)

G. Fey, Hamburg Univ. of Technology (DE)

T. Garbolino, Silesian TU, Gliwice (PL)

M. Keim, Mentor Graphics, Wilsonville (US)

A. Krasniewski, WUT, Warsaw (PL)

H. Kubátová, CTU in Prague (CZ)

H. Manhaeve, Q-Star Test (BE)

A. McEwan, University of Leicester (UK)

L. Miclea, TU of Cluj-Napoca (RO)

A. Miele, Politecnico di Milano (IT)

R. Růžička, BUT, Brno (CZ)

T. Sato, Fukuoka University (JP)

M. Sonza Reorda, Politecnico di Torino (IT)

A. Steininger, Vienna U. of Techn. (AT)

V. Stopjaková, STU, Bratislava (SK)

R. Ubar, TTU, Tallinn (EE)

H. T. Vierhaus, Brandenburg U. Tech. (DE)